1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. The invention particularly relates to a semiconductor device which has a higher withstand voltage and in which the reverse recovery current is reduced, and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
A semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor) is applied to various inverter circuits as a switching element. In order to release the energy stored in an inductive load in the switching process and utilize it as the circulating current, a diode is connected in antiparallel with a main semiconductor device. Such a diode is especially referred to as a flywheel diode.
Excess carriers are stored in a diode in the forward bias state, that is, in the ON state. The stored excess carriers are released in the process of transition to the OFF state, that is, the reverse bias state. At this time, current flows in a direction opposite to the forward direction of the diode. This current is especially referred to as reverse recovery current which flows into a semiconductor device such as the IGBT, resulting in the loss. The excess carriers which constitute the reverse recovery current are, in this case, minority carriers or holes.
A diode in which the minority carriers are not stored is the Schottky diode. Description of the Schottky diode is given below referring to the figure. With reference to FIG. 54, at one surface of an n− substrate 101, a silicon oxide film 107 is formed. An anode metallic electrode 105 is further formed via a Schottky junction region 104. At the other surface of n− substrate 101, a cathode metallic electrode 106 is formed via an n+ cathode region 102.
In this structure, most current flowing through Schottky junction region 104 is constituted by the majority carriers. Therefore, no minority carrier is stored in n− substrate 101, and the reverse recovery current is small. As a result, a high speed switching is possible. However, the withstand voltage in the reverse bias state depends on Schottky junction region 104. The withstand voltage is about 100V at most, and improvement of the withstand voltage is impossible.
In order to improve the withstand voltage, a structure has been used in which a pn junction is provided around the Schottky junction region, a depletion layer extending from the pn junction in the reverse bias state is utilized, and the withstand voltage is obtained. A first conventional diode having such a structure is described referring to the figure. With reference to FIG. 55, a plurality of p anode regions 103 are formed at one surface of n− substrate 101. On the one surface of n− substrate 101 including p anode regions 103, an anode metallic electrode 105 is formed. Schottky junction region 104 is formed between anode metallic electrode 105 and n− substrate 101. On the other surface of n− substrate 101, a cathode metallic electrode 106 is formed via n+ cathode region 102.
In this diode, a depletion layer extends from an interface between p anode regions 103 and n− substrate 101 toward the n− substrate particularly in the reverse bias state. In the vicinity of Schottky junction region 104, the depletion layers extending from the interfaces between the adjacent p anode regions 103 and n− substrate 101 connect with each other, easing the electric field. As a result, the withstand voltage in the reverse bias state is improved compared with the Schottky diode.
A second conventional diode is described referring to the figure. With reference to FIG. 56, a plurality of p anode regions 103 are formed at one surface of n− substrate 101. At regions between respective p anode regions 103, a p− region 108 is formed. On p anode regions 103 and p− region 108, anode metallic electrode 105 is provided. On the other surface of the n− substrate, cathode metallic electrode 106 is formed via n+ cathode region 102.
In this diode, a depletion layer extends from an interface between p anode region 103 and n− substrate 101 toward n− substrate 101, and a depletion layer further extends from an interface between p− region 108 and n− substrate 101 toward n− substrate 101, particularly in the reverse bias state. As a result, the withstand voltage is further improved compared with the diode shown in FIG. 55.
A third conventional diode disclosed in Japanese Patent Laying-Open No. 4-321274 is described referring to the figure. With reference to FIG. 57, a plurality of concave portions 206 are formed at one surface of a semiconductor substrate of one conductivity type 201. A semiconductor region of opposite conductivity type 204 is formed along an inner surface of each concave portion 206. A one electrode metal 205 is formed on one conductivity type semiconductor substrate 201 including the surface of concave portion 206. On the opposite side of one conductivity type semiconductor substrate 201, an ohmic electrode metal 203 is formed via a one conductivity type semiconductor 202 of low resistance. One conductivity type semiconductor substrate 201 and one electrode metal 205 constitute the Schottky barrier junction.
In this diode, a depletion layer extends from an interface between semiconductor region of opposite conductivity type 204 and semiconductor substrate of one conductivity type 201 toward one conductivity type semiconductor substrate 201 in the reverse bias state. At this time, the portion adjacent to the interface between one conductivity type semiconductor substrate 201 and one electrode metal 205 is sandwiched between the depletion layers. Accordingly, in a portion adjacent to one conductivity type semiconductor substrate 201 and one electrode metal 205, the electric field is eased and the withstand voltage is improved.
Next a fourth conventional diode disclosed in U.S. Pat. No. 4,982,260 is described. Referring to FIG. 58, on one surface of a first semiconductor substrate layer 502, a second semiconductor layer 506 is formed. At a main surface 508 of the second semiconductor layer 506, a plurality of trenches 512A–512F are formed. P+ regions 510A–510D as well as mesa regions 514A–514C are alternately provided between adjacent trenches. The depth of p+ regions 510A–510D is substantially identical to that of trenches 512A–512F. Oxide layers 522A–522F are respectively formed at respective inner surfaces of trenches 512A–512F. A metallic anode 518 is formed on main surface 508 of the second semiconductor layer 506. Schottky barrier regions 550A–550C are formed between metallic anode 518 and the second semiconductor layer 506. A cathode 504 is formed on the other surface of the first semiconductor substrate layer 502.
In this diode, a depletion layer extends from an interface between p+ regions 510A–510D and the second semiconductor layer 506 toward the second semiconductor layer 506 in the reverse bias state. The depletion layer extending from each interface is connected with adjacent depletion layers, and the withstand voltage of the diode is improved.
Another diode disclosed in U.S. Pat. No. 4,982,260 is described as a fifth conventional art using the figure. With reference to FIG. 59, on one surface of a first semiconductor substrate layer 702, a second semiconductor layer 706 is formed. A plurality of trenches 710A–710F are provided at a main surface of second semiconductor layer 706. At the bottoms of respective trenches 710A–710F, p+ regions 720A–720F are provided. Respective trenches 710A–710F have their side surfaces at which oxide layers 722A–722J are formed. On the main surface of the semiconductor layer 706, a metallic anode 716 is formed. On the other surface of the first semiconductor substrate layer 702, a cathode 704 is formed.
In this diode, a depletion layer extends from an interface between p+ regions 720A–720F and the second semiconductor layer 706 toward the second semiconductor layer 706. Each depletion layer is connected to adjacent depletion layers, and extends to still deeper region in the second semiconductor layer 706. As a result, the withstand voltage of the diode is further improved.
Problems of those conventional diodes described above are as follows.
In the diode shown in FIG. 55 presented as the first conventional art, holes as minority carriers are injected from p anode region 103 toward n− substrate 101 in the forward bias state. At this time, p anode region 103 includes a relatively large number of impurities, so that still more holes are injected into n− substrate 101 and stored therein. Therefore, the reverse recovery current increases in the process of transition from the forward bias state to the zero bias state.
In the diode shown in FIG. 56 presented as the second conventional art, p anode region 103 has a relatively high concentration, so that still more holes are injected from p anode region 103 into n− substrate 101 in the forward bias state. As a result, the reverse recovery current increases.
When the potential between the metallic anode 716 and cathode 704 in the reverse bias state becomes higher, a depletion layer extends from an interface between p− region 108 and n− substrate 101 toward n− substrate 101, and the depletion layer further extends toward p− region 108. If the edge of the depletion layer has contact with anode metallic electrode 105, the dielectric breakdown could occur.
In the diode shown in FIG. 57 as the third conventional art, after concave portion 206 is formed at one conductivity type semiconductor substrate 201, opposite conductivity type semiconductor region 204 is formed along the inner surface of concave portion 206. Therefore, the concentration of impurities is relatively high in the entire semiconductor region of opposite conductivity type 204. As a result, still more holes are injected from opposite conductivity type semiconductor region 204 into one conductivity type semiconductor substrate 201 in the forward bias state. As a result, the reverse recovery current increases.
In the diode shown in FIG. 58 as the fourth conventional art, the concentration of impurities in the formed p+ regions 510A–510D is relatively high. Still more holes are injected from the p+ regions into the second semiconductor layer in the forward bias state. As a result, the reverse recovery current increases.
In the diode shown in FIG. 59 as the fifth conventional art, the concentration of impurities in the formed p+ regions 720A–720F is relatively high, and the reverse recovery current also increases.